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CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
Rev. 1 -- 21 February 2011 Product data sheet
1. General description
CBTL06DP211 is a multi-channel high-speed multiplexer meant for DisplayPort (DP) v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s or 2.7 Gbit/s. It is designed using NXP proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP211 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. CBTL06DP211 consumes very low current in operational mode (less than 1 mA typical) and provides for a shutdown function (ultra low current consumption less than 10 A) to support power-sensitive or battery-powered applications. It is designed for delivering optimum performance at DP data rates of 1.62 Gbit/s and 2.7 Gbit/s. A typical application of CBTL06DP211 is on motherboards where one of two GPU display sources needs to be selected to connect to a display sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth pass-gate technology), the CBTL06DP211 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. Optionally, the CBTL06DP211 can be used in conjunction with an HDMI/DVI level shifter device (PTN3360A/B or PTN3360D) to allow for DisplayPort as well as HDMI/DVI connectivity.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1a - 1.62 Gbit/s or 2.7 Gbit/s) 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort signals 1 channel with 4 : 1 multiplexing/switching for AUX differential signals and DDC single-ended clock and data signals 1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals High-bandwidth analog pass-gate technology Very low lane intra-pair skew (5 ps typical) Very low inter-pair skew (< 180 ps) Switch/multiplexer position select CMOS input Shutdown mode CMOS input Shutdown mode delivers ultra low power consumption
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor Supports HDMI/DVI incorrect dongle connection Single 3.3 V power supply Very low operation current of 0.2 mA typical Very low shutdown current of < 10 A ESD 8 kV HBM, 1 kV CDM ESD 2 kV HBM, 500 V CDM for control pins Available in 5 mm x 5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board connectors
4. Ordering information
Table 1. Ordering information Solder process Pb-free (SnAgCu solder compound) Package Name CBTL06DP211EE TFBGA48 Description plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm[1] Version SOT918-1 Type number
[1]
Total height including solder balls after printed-circuit board mounting = 1.15 mm.
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
5. Functional diagram
VDD
CBTL06DP211
4
IN1_n+ IN1_n- IN2_n+ IN2_n-
0
4 4
OUT_n+ OUT_n-
1
AUX1+ AUX1- AUX2+ AUX2- DDC_CLK1 DDC_DAT1 DDC_CLK2 DDC_DAT2
00
10 AUX+ or DDC clock AUX- or DDC data AUX+ AUX-
01
11
HPD_1
0 HPDIN
HPD_2
1
GPU_SEL DDC_AUX_SEL TST0 XSD
GND
002aag002
Fig 1.
Functional diagram
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
6. Pinning information
6.1 Pinning
ball A1 index area
CBTL06DP211EE
123456789
A B C D E F G H J
002aag003
Transparent top view
Fig 2.
Pin configuration for TFBGA48
1 A B C D E F G H J AUX- HPDIN OUT_1- OUT_2- OUT_3- GPU_SEL OUT_0-
2 VDD OUT_0+ DDC_AUX _SEL OUT_1+ OUT_2+ OUT_3+ TST0 AUX+ HPD_1
3
4 IN1_0-
5 IN1_1- IN1_1+
6 IN1_2- IN1_2+
7
8 IN1_3+
9 IN1_3- IN2_0-
GND
IN1_0+
XSD
IN2_0+ GND IN2_1+ IN2_2+ IN2_3+ GND
IN2_1- IN2_2- IN2_3-
HPD_2
GND VDD
DDC_CLK2 DDC_DAT2
AUX2+ AUX2-
GND
DDC_CLK1 DDC_DAT1
AUX1+ AUX1-
002aag004
Transparent top view
Fig 3.
Ball mapping
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
6.2 Pin description
Table 2. Symbol GPU_SEL Pin description Ball A1 Type 3.3 V low-voltage CMOS single-ended input Description Selects between two multiplexer/switch paths. When HIGH, path 2 left-side is connected to its corresponding right-side I/O. When LOW, path 1 left-side is connected to its corresponding right-side I/O. Selects between DDC and AUX paths. When HIGH, the DDC_CLKn and DDC_DATn I/Os are connected to their respective AUX terminals. When LOW, the AUX+ and AUX- I/Os are connected to their respective AUX terminals. Shutdown pin. Should be driven HIGH or connected to VDD for normal operation. When LOW, all paths are switched off (non-conducting) and supply current consumption is minimized. Test pin for NXP use only. Should be tied to ground in normal operation. Four high-speed differential pairs for DisplayPort or PCI Express signals, path 1, left-side.
DDC_AUX_SEL
C2
3.3 V low-voltage CMOS single-ended input
XSD
B7
3.3 V low-voltage CMOS single-ended input 3.3 V low-voltage CMOS single-ended input differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O
TST0 IN1_0+ IN1_0- IN1_1+ IN1_1- IN1_2+ IN1_2- IN1_3+ IN1_3- IN2_0+ IN2_0- IN2_1+ IN2_1- IN2_2+ IN2_2- IN2_3+ IN2_3- OUT_0+ OUT_0- OUT_1+ OUT_1- OUT_2+ OUT_2- OUT_3+ OUT_3- AUX1+ AUX1- AUX2+ AUX2-
G2 B4 A4 B5 A5 B6 A6 A8 A9 B8 B9 D8 D9 E8 E9 F8 F9 B2 B1 D2 D1 E2 E1 F2 F1 H9 J9 H6 J6
Four high-speed differential pairs for DisplayPort or PCI Express signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side. High-speed differential pair for AUX signals, path 2, left-side.
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
Table 2. Symbol
Pin description ...continued Ball H8 J8 H5 J5 H2 H1 J2 H3 J1 A2, J4 B3, C8, G8, H4, H7 Type differential I/O differential I/O differential I/O differential I/O differential I/O differential I/O single-ended I/O single-ended I/O single-ended I/O power supply ground Description Pair of single-ended terminals for DDC clock and data signals, path 1, left-side. Pair of single-ended terminals for DDC clock and data signals, path 2, left-side. High-speed differential pair for AUX or single-ended DDC signals, right-side. Single ended channel for the HPD signal, path 1, left-side. Single ended channel for the HPD signal, path 2, left-side. Single ended channel for the HPD signal, right-side. 3.3 V power supply. Ground.
DDC_CLK1 DDC_DAT1 DDC_CLK2 DDC_DAT2 AUX+ AUX- HPD_1 HPD_2 HPDIN VDD GND
7. Functional description
Refer to Figure 1 "Functional diagram". The CBTL06DP211 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the DDC / AUX channel. The detailed operation is described in Section 7.1.
7.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and DDC_AUX_SEL as described below.
Table 3. GPU_SEL 0 1 Table 4. GPU_SEL 0 1 Multiplexer/switch select control for IN and OUT channels IN1_n active; connected to OUT_n high-impedance IN2_n high-impedance active; connected to OUT_n
Multiplexer/switch select control for HPD channel HPD1 active; connected to HPDIN high-impedance HPD2 high-impedance active; connected to HPDIN
CBTL06DP211
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CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
Table 5.
Multiplexer/switch select control for DDC and AUX channels GPU_SEL 0 1 0 1 AUX1 active; connected to AUX high-impedance high-impedance high-impedance AUX2 high-impedance active; connected to AUX high-impedance high-impedance DDC_CLK1, DDC_DAT1 high-impedance high-impedance active; connected to AUX high-impedance DDC_CLK2, DDC_DAT2 high-impedance high-impedance high-impedance active; connected to AUX
DDC_AUX_SEL 0 0 1 1
7.2 Shutdown function
The CBTL06DP211 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL06DP211 is provided. Pin XSD (active LOW) puts all channels in off mode (non-conducting high-impedance state) while reducing current consumption to near-zero.
Table 6. XSD 0 1 Shutdown function State shutdown active
CBTL06DP211
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8. Limiting values
Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tcase VESD Parameter supply voltage case temperature electrostatic discharge HBM voltage HBM; CMOS inputs CDM CDM; CMOS inputs
[1] [2]
[1] [1] [2] [2]
Conditions
Min -0.3 -40 -
Max +5 +85 8000 2000 1000 500
Unit V C V V V V
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 8. Symbol VDD VI Recommended operating conditions Parameter supply voltage input voltage CMOS inputs HPD, DDC/AUX inputs other inputs Tamb
[1] [2]
[1][2]
Conditions
Min 3.0 -0.3 -0.3 -0.3 -40
Typ 3.3 -
Max 3.6 VDD + 0.3 VDD + 0.3 +2.6 +85
Unit V V V V C
ambient temperature operating in free air
HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is placed in series. See Section 11.1 "Special considerations". DDC/AUX inputs are tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and the pin is placed in series. See Section 11.1 "Special considerations".
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
10. Characteristics
10.1 General characteristics
Table 9. Symbol IDD Pcons tstartup trcfg General characteristics Parameter supply current power consumption start-up time reconfiguration time Conditions operating mode (XSD = HIGH); VDD = 3.3 V shutdown mode (XSD = LOW); VDD = 3.3 V operating mode (XSD = HIGH); VDD = 3.3 V supply voltage valid or XSD going HIGH to channel specified operating characteristics GPU_SEL or DDC_AUX_SEL state change to channel specified operating characteristics Min Typ 0.2 Max 1 10 5 1 1 Unit mA A mW ms ms
10.2 DisplayPort channel characteristics
Table 10. Symbol VI VIC VID DDIL DisplayPort channel characteristics Parameter input voltage common-mode input voltage differential input voltage differential insertion loss channel is on; f = 100 MHz channel is on; f = 1.5 GHz channel is off; 0 Hz f 1.5 GHz DDRL differential return loss channel is on; 0 Hz f 1.5 GHz adjacent channels are on; 0 Hz f 1.5 GHz -3.0 dB intercept from left-side port to right-side port or vice versa intra-pair inter-pair DDNEXT differential near-end crosstalk B tPD tsk(dif) tsk bandwidth propagation delay differential skew time skew time Conditions Min -0.3 0 Typ -1.6 -2.7 -35 -10 -40 2.0 100 5 Max +2.6 2.0 1.2 180 Unit V V V dB dB dB dB dB GHz ps ps ps
CBTL06DP211
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DisplayPort Gen1 2 : 1 multiplexer
10.3 AUX and DDC ports
Table 11. Symbol VI VO VIC VID tPD AUX and DDC port characteristics Parameter input voltage output voltage common-mode input voltage differential input voltage propagation delay from left-side port to right-side port or vice versa
[1]
Conditions no load AUX
Min -0.3 0 -
Typ 180
Max VDD + 0.3 VDD 2.0 1.4 -
Unit V V V V ps
[1]
Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
10.4 HPDIN input, HPD_x outputs
Table 12. Symbol VI VO tPD
[1]
HPD input and output characteristics Parameter input voltage output voltage propagation delay no load from HPDIN to HPD_x or vice versa
[1]
Conditions
Min -0.3 -
Typ 180
Max VDD + 0.3 VDD -
Unit V V ps
Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.
10.5 GPU_SEL, DDC_AUX_SEL and XSD inputs
Table 13. Symbol VIH VIL ILI GPU_SEL, DDC_AUX_SEL, XSD input characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current VDD = 3.6 V; 0.3 V VI 3.9 V Conditions Min 2.0 Typ Max 0.8 10 Unit V V A
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DisplayPort Gen1 2 : 1 multiplexer
11. Application information
11.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to occur on pins AUX+ and AUX-, as well as HPDIN. When AUX+ and AUX- are connected through a minimum of 2.2 k resistor each, the CBTL06DP211 will sink current but will not be damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 k resistor. (Correct functional operation to specification is not expected in these scenarios.) The latter also prevents the HPDIN input from loading down the system HPD signal when power to the CBTL06DP211 is off.
CBTL06DP211
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12. Package outline
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm SOT918-1
D
B
A
ball A1 index area
E
A
A2
A1
detail X
e1 e b v w
M M
CAB C
C y1 C y
J H G F E D C B A
e
e2
ball A1 index area
1
2
3
4
5
6
7
8
9
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.15 A1 0.25 0.15 A2 0.90 0.75 b 0.35 0.25 D 5.1 4.9 E 5.1 4.9 e 0.5 e1 4 e2 4 v 0.15 w 0.05 y 0.08 y1 0.1
OUTLINE VERSION SOT918-1
REFERENCES IEC --JEDEC MO-195 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-09-21 05-10-13
Fig 4.
CBTL06DP211
Package outline TFBGA48 (SOT918-1)
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DisplayPort Gen1 2 : 1 multiplexer
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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DisplayPort Gen1 2 : 1 multiplexer
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 5.
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DisplayPort Gen1 2 : 1 multiplexer
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 16. Acronym AUX CDM CMOS CPU DDC DVI GPU ESD HBM HDMI HPD I/O Abbreviations Description Auxiliary channel (in DisplayPort definition) Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit Display Data Channel Digital Video Interface Graphics Processor Unit ElectroStatic Discharge Human Body Model High-Definition Multimedia Interface Hot Plug Detect Input/Output
15. Revision history
Table 17. Revision history Release date 20110221 Data sheet status Product data sheet Change notice Supersedes Document ID CBTL06DP211 v.1
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2011. All rights reserved.
16.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 -- 21 February 2011
16 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
16.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 -- 21 February 2011
17 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
18. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 9 10 10.1 10.2 10.3 10.4 10.5 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Multiplexer/switch select functions . . . . . . . . . . 6 Shutdown function . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General characteristics . . . . . . . . . . . . . . . . . . . 9 DisplayPort channel characteristics . . . . . . . . . 9 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . 10 HPDIN input, HPD_x outputs . . . . . . . . . . . . . 10 GPU_SEL, DDC_AUX_SEL and XSD inputs . 10 Application information. . . . . . . . . . . . . . . . . . 11 Special considerations . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 February 2011 Document identifier: CBTL06DP211

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